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Recent content by ombadei

  1. O

    What does line tagged with 0 and 1 mean in DineroIV trace output?

    Re: DineroIV Trace Ouput does anyone has experience in dealing with dinero?
  2. O

    Help me to run the simulation code in Modelsim

    i am just worried that my system has not enough ram to handle. well.. thanks anyway.
  3. O

    Help me to run the simulation code in Modelsim

    do u mean that it is able to handle large capacity of text? can you show me an example of how to do so?
  4. O

    What does line tagged with 0 and 1 mean in DineroIV trace output?

    I was given the below trace output (only showing the beginning section) from dineroIV cache simulator. The actual trace is roughly 70 over million lines and sized at 500MB. While i can presume that the lines tagged with '2' belongs to an instruction not dealing with main memory, i am not sure...
  5. O

    Help me to run the simulation code in Modelsim

    Modelsim Suppose i need to run simulation code in modelsim that is iterative and it's going to output in transcript window that will exceed well over 100 million lines. Is modelsim able to handle such workload? Also, if i need to view the transcript, is it saved somewhere where i can preview in...
  6. O

    How does ARM's MMU function ?

    Re: ARM's MMU Thanks Amr Ali for something to refer to.. Do you mind explaining the setting of the MMU mapping table for the below code? Would like to grasp a better understanding.. especially what is the wAttrib for? void MMU_SetMTT(int wVSAddr,int wVEAddr,int wPSAddr,int wAttrib) { U32...
  7. O

    algorithm needed, pleae help (vhdl)!!!

    not sure if this will work.. slightly pseudo version..not done vhdl for quite some time.. if i am not wrong.. the below can be done combinationally.. pardon me if it doesnt work for u.. process(start) begin if rising_edge(start) then enableCounter <= 1; //enable 1second counter else if...
  8. O

    How does ARM's MMU function ?

    Re: ARM's MMU can anyone help me out with some insights.. really desperate..
  9. O

    Xilinx FPGA FIFO core

    I have used the coregen fifo quite some time back.... lets see if i can answer you.. Once you generated the fifo through the wizard setup(VHO file).. all you have to do is to treat it like a component.. Instantiate it and declare signals to map it.. then follow the datasheet on the specific...
  10. O

    How does ARM's MMU function ?

    Re: ARM's MMU No startup code.. just program specific traces.. was given virtual addresses that were meant to access the dram.. this trace is an extraction from a cache simulator.. The trace was supplied to me by my ex-supervisor who had left the school.. not much instruction was passed...
  11. O

    How does ARM's MMU function ?

    Does anyone know how ARM's MMU function? Interested in the part on: Given the physical ram size, how does the virtual address gets translated to the physical address(what this address is)? I am doing simulation work here. I was given a standard workload trace (e.g gzip) with virtual addresses...
  12. O

    Need guidance in improving verilog coding skills

    Re: verilog Hi, I need to pick up verilog to perform some simulation for a simple controller.. Do need some advice on this. I have a set of simulation verilog files for the behaviour of a RAM.. It has its own testbench files to call 'task' and perform an operation. Can i create an FSM for a...
  13. O

    System C interfacing to Verilog

    accessing system c models in verilog I am new to SystemC.. For the moment, i am guessing that i just need to create interfaces in SystemC to link to a known processor simulator.. Do i need the verification library SCV and the TLM downloads?
  14. O

    System C interfacing to Verilog

    c to verilog My long term goal is to look at power consumption. So, i guess.. RTL would be the appropriate model.. Hence, what aspects of systemC should i consider?
  15. O

    System C interfacing to Verilog

    mixed systemc verilog What is the difference between RTL and TLM?
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