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Recent content by omar97

  1. O

    problem in metal fill with ICV

    i use this options and everything is ok. signoff_create_metal_fill -track_fill generic -select_layers M2 -fill_all_tracks true -report_density on
  2. O

    problem in metal fill with ICV

    hello sir, that is only two warning massages on icv.log WARNING: Unable to find the script 'rsh'. WARNING: Unable to find program "rsh". Using "ssh" instead. and i think that is no relations with these two massages with adding metal fill. because in icv standalone these two warning messages...
  3. O

    problem in metal fill with ICV

    hello all, i am using technology TSMC 65nm and i reach to final stages, now i am trying to add metal fill to avoid min density violations. i am using ICV (ic validator) to do this on ICC2 using command (signoff_create_metal_fill). here is a problem, when i run this command it takes time to...
  4. O

    Link between calibre and icc2

    PCB ?! I mean ic compiler related to vlsi design
  5. O

    Link between calibre and icc2

    Hello all, I want to know how to open drc violations that generated from calibre on ic compiler 2. Thanks
  6. O

    How to execute metal fill

    Thank you so much. I was check switches well and it's worked.
  7. O

    How to execute metal fill

    I know that, My question is I run filling on metal layers, no thing happened. In TSMC dummy runset, there is many switches, actually we switched on all switches we need and also there is nothing happened.
  8. O

    How to execute metal fill

    Yes, it's for ICV
  9. O

    How to execute metal fill

    i run it on ICV in design on ICC2
  10. O

    How to execute metal fill

    Hello all, I want to make auto metal fill in design using ICV on ICC2. I did everything discussed in ICC2 user manual of how to do this. I am using TSMC 65 nm technology. I used dummy run set as a metal fill run set. And when I run the command to auto metal fill (signoff_create_metal_fill), it...
  11. O

    DRC errors

    Hello sir, Great thanks for your attention. Actually, i have only a few years of experience of working. But i opened the technology file and found that the technology name is TSMC N65 SP9M6x2z TCBN65. So, i decided to choose runset ICVLN65S_9M_6X2Z for ICV or CLN65S_9M_6X2Z for calibre. Is that...
  12. O

    DRC errors

    Hello everyone, I have nearly 400000 DRC errors on VIA7. I am using technology TSMC 65nm with runset M9_6X2Z actually, i can't understand why this errors appeared for me. Can someone help me to understand why this errors appered? this is a complete description of this error: 0: Layer: VIA7...
  13. O

    drc error

    Hello sir, These are screenshots of my errors.
  14. O

    drc error

    Thank you sir, and I will read surah Al waqiah ❤️ ISA. But one thing to take into account I see in layout gui that the spacing actually is very large between Vdd and Vss. Also I see one neighbour standard cell don't get this violation. So, I am not sure is that actually a problem? And also...
  15. O

    drc error

    I face a problem, during powerplanning when I connect power and ground nets to power and ground pins, then when I check pg drc, I get a huge number of drc violations in metal 1 between vdd and vss metals. The drc error is end of line keepout zone violations on metal1 inside standard cell. I...
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