Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
this is code for clock divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mod_326 is
generic(
N: integer := 9;
M: integer := 326
);
port(
clk, reset: in std_logic;
max_tick: out std_logic;
q: out std_logic_vector(N-1 downto 0)
);
end entity;
architecture arch...
this is compare code ...
library ieee;
use ieee.std_logic_1164.all;
entity compare is
generic(W: integer := 8);
port(
clk, reset: in std_logic;
clr_flag, set_flag: in std_logic;
din: in std_logic_vector(w-1 downto 0);
a: out std_logic_vector (4 downto 0):="00000" ;
flag: out std_logic
);
end...
this is uart code ....
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UART_1 is
generic(
DBIT: integer := 8;
SB_TICK: integer := 16
);
port(
clk, reset: in std_logic;
rx: in std_logic;
s_tick: in std_logic;
rx_done_tick: out std_logic;
dout: out std_logic_vector(7...
can yuo help me to detect the error
when i connect the rfid reader with kit doesn't give me the condition i want
>>>>code >>>>>
--RFID TOP-LEVEL DESIGN
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY RFID IS
--I/O PINS
PORT (
CLK, RESET,R_X : IN STD_LOGIC;
A_o: out std_logic_vector...
can you help me ?
i am working in project based on FPGA kit and GSM
i have read the datasheet of GSM900 and i understood its ATcommands
But i don't know how to code it in VHDL
i knew i should have ascii code and shift register
could you show me the steps should i follow it
and if you have a...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
