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can you give assistance on how to do mapping of ports and pins.. I guess pins are names as HEX0, HEX 1 etc you mean to say i should assign or equate these ports to pins
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Do I need to map
output a, b, c, d, e, f, g, dp,
output [3:0] an
to my pin plannar
you are right.. actual code is as under but i am trying to comile and run it using Quatus for Altera DE1 board.. I am new to it. What I thought I have a sample project which has functional and has a pin plannar and qpf file.. What I was trying to do was to embed the test code which i shared...
I am getting error in verilog code while compiling using Quartus II as under
Line 313 is
#50 clock = ~clock;
code for the test bench module is
// Outputs
wire [3:0] d0;
wire [3:0] d1;
wire [3:0] d2;
// Instantiate the Unit Under Test (UUT)
stopwatch uut (
.clock(clock)...
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