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hi,i'm newbie in vhdl and have same problem. i've lookin for error but i can't find it in this code:
process (maxmin_out_sig, reset)
begin
if (reset='1') then
PWM_out_sig<='0';
elsif (rising_edge (maxmin_out_sig)) then
PWM_out_sig<=PWM_out_sig;
else...
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