Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
doubt on extraction
Hi,
What are the types of extraction?
I come across words, like 2D, 2.5D and 3D extraction.
Can any one explain it or share relating docs...
Thank you
sree
hi,
i am unable to realise correct functionality diffrence in the below expressions,
#10 a <= b;
and
a <= #10 b;
i guess in both cases, b value is assigned to a after 10 time units.
please help me out.
regards,
sree
Re: buffer cells vs delay cells in delay matching in placeme
hi,
thanks for your response. i will elaborate my question.
my question is buffers and delays are two diffrent cells available in libraries.
i heard that, for delay insertion/reduction, we generally prefer buffer cells than delay...
Re: Clock Tree Synthesis
in physical design, clock tree synthesis should be done after placement.
add, up/down size buffers to meet your timing constraints...
standard book for verilog are,
1) "Modelling,Synthesis, and Rapid Prototyping with the Verilog HDL" by Michael D Ciletti.
2) "Advanced Digital Design with Verilog HDL" by Michael D Ciletti.
tools are,
1) Quartus II from Altera: free download, but valid for few days.
2)Active HDL from ALDEC...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.