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Recent content by novise

  1. N

    how to practice PERL language

    hey, read PERL cookbook..try wriring some simple tool using PERL
  2. N

    FFT Hardware Implementation

    As far as adders go , if u simply put a plus and let RTL Compiler , it will put an efficient adder as RC is pretty good in carry save optimizations
  3. N

    How to incorporate internal memory(RAM) in a design?

    internal memory how do you incorporate internal memory(RAM)in a design.It should be treated as a hard macro right?how do you take care of it while coding
  4. N

    What are the hard macros which we get in SOC Encounter?

    Re: Hard macros hard macros are blocks,for example RAM that are included in a design without knowing actual functionality.So,while performing DFT,these blocks have to be skipped over.
  5. N

    set up and hold time?

    maximum clock frequency with setup and hold time if hold time is violated,the chip has to be discarded,but,it is only setup time that controls freq of operation
  6. N

    What is the three step algorithm for motion estimation?

    motion estimation what is the three step algorithm for motion estimation?Please send me some links on it
  7. N

    What's the best text editor for Solaris for Verilog coding?

    best editor for verilog gvim is one useful text editor.its pretty good
  8. N

    What do the terms fan-out and fan-in mean?

    fanout calculation ttl logic gates fanout is the maximum number of gates of the same family that a gate can drive
  9. N

    help on motion estimation algorithms

    hi, can somebody give me some info on the currently used motion estimation algorithms
  10. N

    assignment statement in Verilog

    a delay can be simulated but it can't be synthesized so it is generally best to avoid delays while coding
  11. N

    what is the difference between #1 a<=b and a<=#1 b

    when #1a<=b is used b(t) is assigned a at time t+1 ,on the other hand when a<=#1b is used b(t+1) is assigned to a at time t+1
  12. N

    asic implementation of the proposed FSBM algorithim for ME

    The FSBM algorithm puts forth an architecture which involves an overlap in the functioning of the processing element. This overlap seems redundant. Any ideas on how to remove this?
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