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Recent content by nomigul

  1. N

    is nested for loop supported in verilog getting this error while using loop inside a for loop

    I have checked the net type reg also but getting same error
  2. N

    is nested for loop supported in verilog getting this error while using loop inside a for loop

    I am using ISE Design Suite 14.5 to try and synthesize a design and I keep getting the following errors while simulation behavioral model Code: module genvarexaplecode(a,b,y ); input [3:0]a,b; integer mem[0:3][0:3]; output [1:0]y; genvar i,j; generate for (i=0; i<4; i=i+1)...
  3. N

    [SOLVED] syntax error generate statement

    I am using ISE Design Suite 14.5 to try and synthesize a design and I keep getting the following errors when trying to use a generate block module genvar(x,y,z ); parameter n = 4; input [n-1:0]x,y; output [n-1:0]z; genvar i; generate for (i=0; i<n; i=i+1) begin xor g1(z1(i),x(i),y(i)); end...

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