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Recent content by no_mad

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    UPF in FPGA

    Noted. Sorry, my bad. Actually, I'm starting to work on FPGA prototyping with UPF. I would like to understand how those power strategies, for example, isolation strategy, retention strategy, and power switch are implemented in FPGA and how do you verify those strategies in the FPGA platform...
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    UPF in FPGA

    Hi guys, Anyone have any experience enabling UPF in FPGA. I have a lot of questions, so I would like to get some inputs and feedback. Please help me out here. Thanks!
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    Suggestion: Low Power Section

    Thank you for your prompt reply. Actually, I don't have any links or specific forum to provide to EDAboard other than vendor tools forum. But this vendor forum specific to their tool. Honestly, this website has helped me to build my career in ASIC design and still does. Last year, I took up...
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    Suggestion: Low Power Section

    Hi, My suggestion is to add new section under "Digital Design & Embedded Programming" called Low Power Design and Verification This new section will also cover power management and power strategy. It will be an interesting topic to discuss. Thanks n regards, No_mad
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    [SOLVED] UPF: merging 2 (or more) power gated domain

    Hi, How can we identify 2(or more) power gated domains have same power characteristic? This is to reduce the number of power gated domain in a partition. Please help me out here. Thank you
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    FishTail: Industry Leading timing exception constraint verification??

    Hi guys, Do let me know what do you think of this topic. Does FishTail is the industry leading in the verifying timing exception constraint? I heard about GCA (Galaxy Constraint Analyzer) from Synopsys and never try it before. To those have experience in running and verifying timing exception...
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    [SOLVED] question on vcs -f filelist ?

    Here is one way to do it: 1) Compile your C code with GCC or G++ 2) Next, if the C code was compiled with x86_64 bit. Thus, to make it VCS simulator compatible with the generated C library file (*.o, *.so) use this line of command: vcs -full64 -sverilog -R +define+VCD -f ../../sim/filelist.f...
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    System Verilog: Virtual

    Thanks Dave. Now I can continue my journey to be System Verilog with OVM expert...my personal goal. My first step is understanding OOP in System Verilog. I read your article on classes. That is really good article. Thanks -no_mad
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    System Verilog: Virtual

    Hi, I'm new in System Verilog with OOP. Here is my question. What's the motivation of "virtual" in SV OOP? ⇒virtual method ⇒virtual class Can someone please explain this to me. Why We need "virtual" ?? Please help me out here. Thanks -no_mad
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    [SOLVED] question on vcs -f filelist ?

    Hi, What was the error message? thanks.
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    How to compile and perform simulation on System verilog with DPI-C call using VCS?

    Hi Nilesh, Good to hear that you are also doing this :) Anyway, here how I does it: 1) First u need to generate your *.so file: >> Example: g++ -Wall -m64 -g -fPIC your_cpp1.cpp your_cpp2.cpp -shared -o your_gen.so 2) VCS compile: >> Example: vcs -debug_all -full64 -sverilog -R...
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    New to Synthesis,require help

    Hi, The best way is if you have an access to use any synthesis tool, write a simple HDL code and try to synthesis. Also, keep a good reference book about synthesis with you. Second is Google :)...then, any issues or doubts, you can post it here. All the best and enjoy!!
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    Looking for emulation and transactor group/forum

    Hi guys, Anyone knows any emulation or transactor groups or forum? Please advice. thanks in advance...
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    How to compile and perform simulation on System verilog with DPI-C call using VCS?

    Hi all, I'm new to SV+DPI-C environment. I'm using VCS for simulation. Question 1: What are the options in VCS to compile C-code together with SystemVerilog codes. Please shed some light. Thanks in advance
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    VI: How to add a prefix to every line? (such as # or //)

    Yes, i got it. Highlight the lines, then type this command :'<,'>s/^/#/g It works. Thanks for your help.
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