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Recent content by nnmate

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    how can man build a MIM or Sandwich-Capacitor by oneself in Cad/Virtuoso

    It's a similar question to this one, https://www.edaboard.com/threads/13886/ but there would be asked with LEDIT. Can some one share the exeperience once making those caps? had already draw the layout. Don't know how to defince terminals and do LVS ...Extraction and LVS check are always...
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    how to realize an FSM for Verilog-A for simulations with Spetre - behavior level

    Hi all, Does anyone here know, how to realize a Finite States Machine by Verilog-A for Cadence IC Tools? I have already got .vhdl file with lines like " variable next_state: states; variable current_state: states;". Donno how to do it with verilog-a to generate a behavioral model...
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    VHDL compiling error with "not " operator : expression is not of type IEEE BALABALA

    Re: VHDL compiling error with "not " operator : expression is not of type IEEE BALABA Hi Tricky, thanks a lot for your reply. I was not saying std_logic=bit=std_ulogic. I surely know and have used ieee.std_logic_1164.all. Then I changed the comic vlvector vlbit into std_logic_vector and...
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    VHDL compiling error with "not " operator : expression is not of type IEEE BALABALA

    VHDL compiling error with "not " operator : expression is not of type IEEE BALABALA Hi all, by compiling a VHDL FSM file I met a serie of errors which said expression is not of type IEEE.STD_LOGIC_1164.STD_ULOGIC, direct at my not operator for a bit input signal. the code is on the website of...
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    LEF file loading error by Encounter 8.x

    thanks alot. The lef files are from the foundry, not generated by myself. Donno what exactly do? should I place two lef files in the blank for Lef files? Or I must edit them?
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    LEF file loading error by Encounter 8.x

    Hi all, I face a loading error which is with the log scripts: Loading Lef file /usr/local/DesignKits/XFab/XH035_IC6_2010-09/cadence/xh035/LEF/xh035_m4_FE/D_CELLSL_HD_mprobe_m4.lef... ERROR (LEFPARS-1505): MANUFACTURINGGRID statement was defined before UNITS. Refer the LEF Language Reference...
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    offset current of an opamp

    ye, I know that. Thank you. So the BJT OP suffers larger offset current at the input stage than the case with CMOS?.... Look forward to your answers LvW and Keith, Thank you again NN
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    offset current of an opamp

    Thanks Keith, I may want to know, in which range can we reduce the offset current, while designing an opamp. Can we reach the pA range?
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    offset current of an opamp

    I´m facing an issue from a textbook which says, for some worst cases, we need an amplifier with offset currents in the 0.01 pA range, (which may be hard to realize?) My question is, how much is a normal offset current for an NMOS Gate input differential amplifier? Is it no other than the gate...
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    Hi, Pseundo Random Bit Stream by Cadence Virtuoso

    Thank you so much! I have a problem which is, the random bit rate should be differential. how can i create differential PRBS. Is there a inverter with no delay and convertng the Generators output (low 1V High 1.5V) to (Low 1.5V High 1V)? Thanks. ps i cant use 2x Generator, because they are...
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    Hi, Pseundo Random Bit Stream by Cadence Virtuoso

    Hello all, the topic is as mentioned in title, how can i generate a PRBS sequence in Cadence virtuoso (or Spectre?) I m first using Cadence, By Hspice it is rather easy with writing script such as V1 PRBS 0 1 ,,,balabala Is there a similar script log for me to input these signals? thanks...
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    Hello, help for literature about circuit design

    thats exactly what i wondered. Since this is a case- dependent study, books describing those relationships could be written. Opamp are always with tradeoff between rf-properties and gains and so on, so we study each circuits and compare the (dis)advantages. its just because that those books are...
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    Hello, help for literature about circuit design

    Hello everyone, i am designing an interface circuit for differential signals, such as cml, lvds at the moment. At college i ve learned so much in analog world, and however, find that, the analog design for digital signalling is totally others... designing an differential amp for LVDS receiver...
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    Hi all, a question about process standard in Sansen's book

    Re: Hi all, a question about process standard in Sansen's bo thanks and merry xmas! could not hope for a better reply.
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    Hi all, a question about process standard in Sansen's book

    Re: Hi all, a question about process standard in Sansen's bo hi erikl, thank you very much for ur replying i know exactly the situation by foundry that u described. i think, it is better to modify my question like this, why do people use p-substrate usually, which advantages do we obtain, when...

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