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Recent content by nizamalphas

  1. N

    Verilog - generate multiple interconnected modules

    how can i decode those 5 input variable into only one variable, i am still new in this thing, need to learn from you all the experts
  2. N

    Verilog - generate multiple interconnected modules

    but it is a 5bit output, and it will display 0 - 31, how can i do this?..mean by using two 7 segment display?..
  3. N

    Verilog - generate multiple interconnected modules

    Can anyone help me, how can i make the output of Sum1, Sum2, Sum3, Sum4, Cout4 in a 7segment display..this my example of verilog hdl program... the submodule.....
  4. N

    4 bit full adder in verilog

    how can i interface the 5 output of 4bit full adder into 7 segment display, anyone can help me?
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