Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Basically in the 0 current situation, you want the positive feedback to be strong. For that you are keeping the current mirror ratio for both PMOS and NMOS >1.
While this should always work, there is the situation of true 0 current. Where still 0 x Large Mirror Ratio = 0. So in theory you would...
One thing you would want to check is how your PVT corners are defined.
With your PTAT bias version, your frequency is a function of 1/(R x C x Vth)
In your process corner file, can you independently vary R, C and Mos corners?
Also, I am guessing here with the limited info, in the LDO version...
Your zero current state depends on a bunch of things to happen together.
Vds mismatch in the PMOS Mirrors will cause the currents to be different by default, causing positive feedback to be stronger.
Vth mismatch in the NMOS Mirrors due to different Vsb will also cause the currents to be...
I am not sure what you mean "without VSS" I am guessing a negative VSS.
But any way, as you would have been taught, the critical specification for this would be Input Common Mode Range.
What is the range of inputs your OPAMP can expect to work with? Is it Rail to Rail (0 to VDD) or more...
1. Back calculate the Open Loop Gain and Bandwidth Specification.
2. Also check the Input and Output Common mode Range. (Rail to Rail input/output or anything else.
From 2 you can decide whether you need NMOS input or PMOS input or both(rail to rail)
From 2 you can also figure out whether you...
I "think" fundamentally you are trying to apply KCL/KVL type DC equations to a system which has loops.
When there are loops, we have to look at causality. And a system which is has right half plane poles will be non-causal.
By my understanding we cannot apply regular DC equations here.
( We can...
You need a True Bipolar ADC
Something like this https://docs.rs-online.com/47ff/0900766b80e41b26.pdf
Or shift/translate your input to the levels of the ADC that you have using some bipolar opamps and such.
In a BGR, there is going to be 2 loops.
The Positive Feedback Loop,
The Negative Feedback Loop.
When you run the stb analysis, ensure that you are breaking the right loop. (ie. inserting the voltage source at the right loop)
Also, at the steady state operating point, your positive feedback...
If you see the structure of your opamp, basically it is opposing current sources.
You have Ibias2 and PM0 and PM1 sourcing current and NM8 sinking it at the bottom.
Just imagine what would happen to the center voltage if a current source and a current sink are in series and their values are...
Tell you boss that you'll need 10mA to keep your design stable with the unknowns and they will come back all the information you need.
Unless you are the boss...!
Just check the Ibias1 and Ibias3 in your bias circuit. Are they in the exact proportion that you expect them to be in? They are not cascoded either.
In the video they have not used any bias circuit but seem to have used very absurdly specific sizes to balance the circuit. 1.799u and what not...
If you consider individual Pass stages for each SRAM, then your load cap is not large. It is just unknown (for now).
The FVF loop will provide a fast loop for transient. Since you load is digital, the load regulation need not be accurate.
Consider the Fig3 in the FVF paper I linked above. ere...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
