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Recent content by nishanthp68

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    Difference between Logic and Reg in System verilog

    Hello , Logic and Reg in System verilog are 4 state variables and are of user defined size . What is the difference between them .If none what is the use of having two data types?
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    Clock Frequency Division with varying frequency

    I have a main clock . I should divide the clock according to the number present in a 32 bit register which keeps on varying at regular intervals . Can some one suggest me how this can be done ?? The duty cycle of the new clock should be 50 % or anywhere close. I tried in the following manner ...
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    State Variable Mapping

    Can anyone tell me what state variable mapping is ?? Also some material would be useful Thank you in advance,
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    Verilog efficient coding

    I was going through some verilog stuff , I came across this . I dont have a clue ,Can anyone help me what the author is trying to say Just as it is important to write code at a level of abstraction where vectors are the primary data type, it is also important to write code which does not...
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    Use of Macros in verilog

    Can anyone please tell me where exactly macros is used and what are the advantages of using macros??
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    dynamic re-use of Intellectual property

    can anyone tell me about dynamic re-use of Intellectual property? Need details
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    meta stable state of a design

    What is a meta-stable state? What can be done to design around it? What precautions should be taken when sending signals between flip-flops on different clocks?
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    Determining Long path during debug

    Can a long path be determined during debug by increasing or decreasing temperature?
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    Difference between Verilog simulators

    what is the difference between IVerilog and NC Verilog ?? How is it that the same verilog code runs differently on different simulatos?
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    Pipelining to make the circuit work faster

    Thank you guys for your help , I am still very new to programming I had not run the program before , I just had done it theoretically integer ix; always @(*) begin res=0; rv=0; diff=Diff; for(ix=0; ix < 24; ix=ix+1) begin rv = { rv[22:0], diff[47:46] }; diff={ diff[45:0],2'b0}; if( {...
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    Pipelining to make the circuit work faster

    That was very helpful , but still I cannot get my timing considerations, can i place two pushout signals within one iteration?
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    Pipelining to make the circuit work faster

    /The circuit synthesizes for 2 Mhz clock need to make it synthesize able for 200 MHz clock // This module calculates the positive circle coordinate Y given X // with a radius of R // It is not very well written, but this provides students with // an opportunity to improve the design :-) //...

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