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Recent content by nine8

  1. N

    What basis floorplanning has to be done?

    i/o pad power netwok macro and module location ?
  2. N

    Regarding output delay /set_output_delay/.

    Regarding output delay. -ve ? what does it mean ?
  3. N

    LOCKup & SYNC Registers.

    functional lock up latch lock-up latch is used in DFT, it 's the solution for the hold time violatiion . add lock-up latch in the scan -chain
  4. N

    please help, Design compiler problem

    are you sure VHDL format file can be loaded into design by "read -format vhdl" command ?
  5. N

    questions about Delay Chain

    you can use "delay cell" whose W/H is less than one.
  6. N

    Where Can I Find Some Free IP Cores?

    QQ Group :13934768 嘿嘿
  7. N

    Why do you specify input and output delays when doing synthesis in Synopsys DC?

    Synopsys DC problem? they are both the margin for the external circuit
  8. N

    Logic Synthesis & Physical synthesis ?

    physical syn will do the virtual floorplan first, and then i can calculate the wire delay vaule which is near to the real floorplan, so the resule it's very Added after 1 minutes: physical syn will do the virtual floorplan first, and then i can calculate the wire delay vaule which is near to...
  9. N

    how to change timescale of SDF in Primetime?

    sdf time scale i think you can change timescale in the testbench right ?
  10. N

    why the DFT test_clock ;s duty cycle is 10%,not 50%?

    in DFT, the test_clock period is 100ns , and duty cycle -timing {45 55}, why not {0 50} ? :D
  11. N

    can anybody talk about "Clock Gating"

    can anybody talk about "Clock Gating" or send me some documents about it ? playearh@gmail.com thx !:D
  12. N

    who can share some documents about Place&Route?

    now ,i am learning APR but i have less documents about it can someone share your documents about it ? Thx !:D
  13. N

    a APR problerm of Synopsys Astro

    Thx i 'll try it ,and then give you the replay ! thx ,again !
  14. N

    a APR problerm of Synopsys Astro

    unit lib and tech file astro Thx ,all To wkong_zhu, i only have smic18_fram ref and other steps are OK. ========================== TO shankarmit i see there is a file called "unitTile_1" in the folder named "CEL" , i dont konw if it's correct ! ========================= 俩个朋友都是中国人吗？
  15. N

    a APR problerm of Synopsys Astro

    synopsys astro who can help me ? Thx
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