Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi,
I have generated layout from schematics,
now I wanted to do DRC using assura,
I am using umc65nm technology,
But i don't know where to copy or install rule file,I am getting error in path directory,
So please explain me how I can install rule file.
hi,
I am designing D FF,
but i know rise and fall time so how to decide Width of NMOS and PMOS to achieve that delay.
Is there any method or only we have to do try and error?
please reply urgent.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
