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U can use the q-7 numbering format. It is an 8-bit system where msb = -1 and the bits to right are negative powers of 2.
eg : -1 2^-1 2^-2 2^-2............2^-7
u can represent numbers ranging from -1 to 0.99
resolution function required
Your internal signal may be driven by two or more sources. In such a case an arbiter is needed to decide which signal to assert on the bus/wire. In VHDL this is done by defining a resolution function.
Refer any decent VHDL reference book for more details.
Re: Issues in vhdl coding...plz let me know if u r aware....
No you cannot use 'wait', or other such delay statements either. There is no way to introduce such timed delay directly.. We have to depend on the 'clock'.
And moreover, using 6 DCM's causes jitter accumulation.
I didnt understand...
Re: Issues in vhdl coding...plz let me know if u r aware....
I went through the code. I found some issues.
1.) In buf_soc and buf_eoc.. you have made the following assignment
O <= I after D_SOC
O <= I after D_EOC
In VHDL 'after' statement is non-synthesizable. But XST...
fatal error unisims/unisim_vital
I cant see why a divide by zero error should occur. Have you properly instantiated the DCM ? With proper feedback ? Have tried using modelsim instead of ISE simulator ?
If possible, upload your VHDL code, or gimme a link if u've already posted it.
cannot continue because of fatal error vhdl
I believe, you had the same error while debugging your DCM (another post of yours).
I can see a mention of "divide by zero" in the error...
Does your testbench perform any such operation ?
top module in vhdl
As far as i know.. u cannot port-map inside a process. Port-mapping is done outside the process.
It doesnt make sense to port-map inside a process. Since you are "describing" hardware, making it 'sensitive' to some clock signal doesnt make sense. The described hardware wont...
hello everyone. Soon i'll be applying for grad schools. My interest lies in FPGAs. Most graduate programs are titled as
1. Integrated Analog Circuits
2. Integrated Digital Circuits
3. CMOS VLSI
4. VLSI Signal Processing.
All i want to know is which of the above courses(or any other) would...
I have done a project on DCT too. But i found, using fixed point notation to represent fractions is more efficient for FPGAs since DCT isnt very sensitive to accuracy issues.
The outputs of the FSM, are actually async reset signals to other modules.. Since they are async, i cannot afford the glitch. Also i cannot afford the delay of an extra clock cycle.
I guess, if i change the resets to synchronous resets, it might solve the problem.
I have designed an FSM with generates output signals (single bit).
The problem is, the outputs are undergoing transitions (picosecond wide transitions) even when i am not intending it.
Im attaching my code,testbench, and a screenshot of the post PAR simulation.
As you can see, outputs are...
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