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Does anyone have any idea how to tradeoff between UGB Phasemargin & DC Gain for a single ended folded cascode differential + Common gate stage?????????
Task is to design a folded cascode with single ended output[Differential amplifier + common gate stage]
Conditions required are:
Technology TSMC 180nm technology*
VDD 3.3
CL ≥ 500fF
Current mirror ratios ≤ 20
Power Dissipation ≤ 3mW
DC Gain ≥ 80 dB
UGB ≥ 600 MHz
Phase margin ≈ 55 degree...
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