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Recent content by niezimei

  1. N

    voltage reference problem

    there are two feedback loop:a negative(N2,P3,P1,R,N1) and a positive (N2,P3,P2).The loop can work only when negative feedback is dominant (R*gmn1>1).Add a cap to split the two poles for stability.
  2. N

    How to improve bandgap PSRR without changing topology or layout?

    bandgap spur enlarge your loop gain since the PSRR in low frequency is too low.
  3. N

    Bandgap @ 0.9 and 2.1 V for ADConvertor

    voltage buffer will be appreciated.
  4. N

    The size of pmos pass transistor in LDO regulator

    pmos pass transistor saturation ldo when pass transistor operates in triode region the loop gain will decrease drasticly.In order to get a reasonable gain error, make sure the loop gain is larger than 60db even at worse case.
  5. N

    Can you build an on-chip LDO ?

    capless ldo It's easy to fix. Use Kelvin Connect
  6. N

    what's the prolem of my bandgap?

    1. mismatch 2.input offset
  7. N

    any kind or bias circuit?

    wrong. The upper should be current mirror rather than current source.
  8. N

    Problem with output voltage of integrator (Spectre)

    integrator hi , I am afraid that you made sth wrong. The circuit can work properly only when the op is powered by two power supply----a postive one and a negative one.Since Vout should be a negative voltage.
  9. N

    Help me to understanding this

    there is an error in your input stage connection.This is a rail-to-rail input current mirror OTA with buffer stage to drive large cap load.
  10. N

    A question about bandgap reference,please help me.

    In my opinion, it is caused by the simulation options. ues method=gear, the parastic ring will disappear.
  11. N

    what is the purpose of these transostors..?

    for ESD protection
  12. N

    Question about LDO and big capacitance between bandgap and gnd

    Question about LDO 1. stablize the loop. 2. smother the load transient. 3. short the ac ripple to ground.
  13. N

    About line regulation of LDO

    As far as I am concerned Vout always rise when Vin increases.
  14. N

    How to choose the single stage OP with gain boost?

    low voltage cascode Vmin=2Veff
  15. N

    BJT in a CMOS tech, Can it be??!

    If your process have twin wells, then you can use both pnp and npn, although their performance is not good enough.
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