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Thanks for your replies.
It seems like I am quite free in choosing Vramp and reference level as I realise that the error amp stage will figure out where to regulate relative to the ramp to produce the desired output voltage, given that it has enough gain to work with.
It also looks like having...
Hi
I am looking into a PWM buck design but having some struggles with understanding how to decide the ramp amplitude, reference voltage and modulator gain and their relation.
The modulator voltage gain is defined as Av_mod = Vin / Vramp
This I understand as the input voltage times the change...
It is a poor description from me regarding the feedback network: it is operating with unity gain and no resistor divider in the feedback network, therefore nothing will draw a significant current if there is no load.
The plan is to have a fairly standard architecture with NMOS diff pair +...
Hi
I am working on a LDO design that requires a rather large PMOS pass transistor due to the specified max current.
I have issues with pulling the pass transistor gate high enough at no load conditions to avoid the output voltage creeping upwards due to leakage in the pass transistor.
In...
So according to theory the resulting input refered will be reduced by half to 30 nV/sqrt(Hz)?
The reason why i'm asking is that im simulating the individual stages to be 58 nV/sqrt(Hz) and 67 nV/sqrt(Hz) individually.
And when im simulating them in parallel i get 56 nV/sqrt(Hz).
Does that...
Hello
I'm a bit unsure on how to calculate the input-refered noise for two OTA in parallel.
Lets say that both OTA have a input referred noise level of Vn = 60 nV/sqrt(Hz) individually.
I have read that if I regard two noise sources connected in series as uncorrelated i can add them.
If i...
Ahh I see, thanks man.
By looking trough the noise summary I found that the strong noise sources were caused by the big resistors used as part of the ideal common-mode feedback.
Hello
I have been getting some strange results when trying to do noise analysis on my opamp design.
The frequency characteristics looks ok when doing stb analysis with unity gain at 1 MHz with 65 degree phase-margin, and behaves nicely in transient.
When doing the noise analysis i see a...
I see.
That is what i am observing.
If I connect a current source at the output to start sinking current, the PMOS will start to deliver current to the output.
I understand the circuit as that the gate drive will then start to decrease for the NMOS and increase for the PMOS.
What I now see...
Hello
I am considering using the topology shown in "A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries" for implementing a class AB output stage.
It is stated several places that this topology is suited only for moderately low voltages...
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