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For the two seperate clock domains, my logic was that I wanted to generate data on the sysClk. However, with bit transitions at each rising edge, my dds would not be able to keep up. Should I incorporate flow control instead? As for the overflow, I'm simply adding the I and Q legs for the IQ...
Hello everyone,
I have designed a simple QPSK modulator and there are a few issues with my design that I am not sure how to fix, partly due to how I designed my DDS. I designed the modulator in two ways, the first using rotation flags based on whether the even/odd bit is 0/1 and the second...
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