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Recent content by newmedi

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    OSC phase noise modeling, veriloga model generation, and verification

    Hello, Is there any workshop material which work through oscillator phase domain modeling and verification? May be the flow will be something like this. 1. circuit simulation with .hb .hbnoise. 2. n, fc, c extraction from the simulation. 3. veriloga modeling 4. comparison of the veriloga...
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    Excluding some circuits from the hSpice MC simulation

    Hello, Is there a way to exclude some circuit from the MC simulations. I know spectre has a option, but I could not find the equivalent one in hspice. Thank you!
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    SERDES termination methods

    I noticed some products have a option to have external or internal capacitive coupling. Is it because of the bandwidth limit?
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    SERDES termination methods

    Klaus. You are right. I was looking at different pdf. https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf Yes. termination didn't change. The termination voltage changed. Again, I'm not a SERDES expert. I just want to learn.
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    SERDES termination methods

    Thank you all. Please understand my newbie questions. I think this is a reasonable document to look at https://www.xilinx.com/support/documentation/user_guides/ug581-ultrascale-gtm-transceivers.pdf It seems the termination method changes based on the protocols.
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    SERDES termination methods

    Hello FvM, Yes. I wanted to do that. However I'm not familiar with SERDES standard organizations and document. I know I can get DDR4/5 standards from JEDEC website. How do I find SERDES standards? If you can point me one, that will be very helpful. Thank you!
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    SERDES termination methods

    Hello all, I have a question about the SERDES terminations methods. In the DDR world, we have different termination specs for LPDDR, DDR3(SSTL), DDR4/5(POD). Is this the same story in SERDES world? Are PCIe, SATA,XAUI, etc having different terminations? Where can i find the summary of those...
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