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Hi Velu,
report_power in ICC, can help you analyse the leakage power.
report_power_calculation will report the voltage and then you can calculate the leakage current in the design.
I hope this is useful.
Hi RGR,
The trial 1 and trial 2
it depends upon following
1. what is your block size.
2. Power requirement of the block.
3. CTS structure to TOP clock structure.
...
Hi Gaurav,
Challenge can be many I would specify few.
1. Placement : As frequency increase then PD engineer gets shorter time period per cycle b/w FF which will result in tight constraints... Need a placement strategy by PD engineer.
2.. CTS... If your placement is not good then you have high...
Hi,
Clock net are heavy loaded mean..... as every individual clock net see multiple Clock input pin in devices i.e. FF . and each nets have it own capacitance to meet the timing requirement. like c-to-q delay... to meet timing one do changes like ( Insert a buffer or sometime resizing present...
Don't consider it to be a square wave, let it be a sine wave with amplitude varying from 1 to -1 ........
Amplitude is not my concern here..........but how to connect its frequency with the phase.
I just wants to knw abt , when a vendor think of implementing a project on a DSP processor and when on FPGA !!!
---------- Post added at 04:01 ---------- Previous post was at 04:00 ----------
I just wants to know , when a vendor thinks of implementing a project on dsp and when on fpga!!!!!!!
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