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I have designed a 10 bit pipelined ADc in cadence.From the wave forms I have obtained the. csv file which contains samples[35,000 values] of the 10 digital bits and inputs. How can we link this to matlab so that these codes are read and hence the inl and dnl plots are obtained??
i am not able to view the DRC ERRORS. Once DRC is run, the error window is not opening. It is actually running,error window alone does nt open up.Once it has been run , it is not possible to run it afterwrads.. , they will show the window that DRC running is in progress, do you want to stop it...
I have my AC magnitude as 1 from the beginning itself...
By changing the biases i was able to achieve gain upto +22.45 dB. but the expected gain is 80dB.
i am a beginner in cadence...
while finding AC gain and phase , when i choose vout/vin i get a negative 32 DB..when i choose vin/vout i get a positive DB.. But gain calculation should be as Vout/Vin. What should i do to make my gain positive.. plz help
I am a beginner in Cadence,I am designing a two stage OTA. My design has folded cascoded configuration in the first stage with class AB along with current mirrors in the 2nd stage.I have attained saturation for all transistors except for one,which is now operating in linear region. My output...
i am a beginner in Cadence and trying to design a 2 stage MOSfet. Is it necessary that all stages should operate in saturation region for amplification..plz help...
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