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Recent content by ncj

  1. N

    Area for pipelined ADC- cadence analog

    I have completed the layout of a 10 bit pipelined ADC.Now i want to find the area of the design. Someone please help me to fi nd the area....
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    [SOLVED] linking matlab and cadence to obtain inl and dnl

    I have designed a 10 bit pipelined ADc in cadence.From the wave forms I have obtained the. csv file which contains samples[35,000 values] of the 10 digital bits and inputs. How can we link this to matlab so that these codes are read and hence the inl and dnl plots are obtained??
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    DRC window not visible in cadence

    i am not able to view the DRC ERRORS. Once DRC is run, the error window is not opening. It is actually running,error window alone does nt open up.Once it has been run , it is not possible to run it afterwrads.. , they will show the window that DRC running is in progress, do you want to stop it...
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    analyses of a pipelined ADC

    can someone plz help me with the formulas to find the SFDR,SNDR,INL, DNL etc for a pipelined ADC in Cadence Software...
  5. N

    calculating gain in cadence

    Thank you... My design is a stage OTA with a folded cascoded first stage and current mirrors in the second stage..
  6. N

    calculating gain in cadence

    I have my AC magnitude as 1 from the beginning itself... By changing the biases i was able to achieve gain upto +22.45 dB. but the expected gain is 80dB.
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    calculating gain in cadence

    i am a beginner in cadence... while finding AC gain and phase , when i choose vout/vin i get a negative 32 DB..when i choose vin/vout i get a positive DB.. But gain calculation should be as Vout/Vin. What should i do to make my gain positive.. plz help
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    finding dc gain in cadence

    I am a beginner in cadence, how to find DCgain in Cadence....?Is it same as the result obtained in AC gain? Plz help....
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    Gain of two stage OTA

    I am a beginner in Cadence,I am designing a two stage OTA. My design has folded cascoded configuration in the first stage with class AB along with current mirrors in the 2nd stage.I have attained saturation for all transistors except for one,which is now operating in linear region. My output...
  10. N

    MOSFET saturation in cadence

    thank you....and i am having difficulty in making them all in saturation....plz help with some solutions...
  11. N

    MOSFET saturation in cadence

    i am a beginner in Cadence and trying to design a 2 stage MOSfet. Is it necessary that all stages should operate in saturation region for amplification..plz help...
  12. N

    feedback factor in an opamp

    what will be the feedback factor in an opamp ???how to find it??
  13. N

    difference betwen maximum output swing and maximum differential output

    what is the difference betwen maximum output swing and maximum differential output swing?? plz help thanks in advance
  14. N

    cmfb voltage that is to be fed to the first stage

    while dseigning,an op-amp,how to decide the cmfb voltage that is to be fed to the first stage of the op-amp?

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