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WINFEKO ERROR!!
While running a code of Patch Antenna, I am getting an error:
Segmentation error, that is two triangles are touching each other but have no common vertex. How do I remove this error.
I am using Xess SV board V1.1, using Parallel Port.I am getting an eroor "cable connection failed "When trying to download via ISE . On using GXLOAD I am getting an error again . How should I download my code on the FPGA?How can be change the direction of Parallel Port ,making it unidirection?
I am using Vertix XCV50 (XESS BOARD V1.1) ,on configuring the device i get an error of "CABLE CONNECTION FAILED",What should i do in order to configure the device?
I am using Xess Board XSV Board V1.1.I have only DB25 Cable.
1. Should I Configure PROM,ACE or JTAG(Boundary ) , I am using Boundary Scan option to generate SV file .
2.Via Parallel port iam using Vertix or CPLD of the board?
3.I am not able to Configure th edevice getting error "CABLE...
What is the difference between TLIN and MLIN?
In practical desizing we use what?
In Filter Design we can make Matching Networks via TLIN, How to convert TLIN into MLIN,if required?
MICROSTRIP
Suppose I design a Low Pass Filter for S band and use Microstrip for capacitors ,Will the length of the Microstrip play any role or only Thickness, Height and Permitivity is important...How will I determine the capacitance of the Microstrip?
XCV50 VERTIX
I Want the UCF File of XCV50 Vertix....
Which has a list like
# Pushbuttons
NET "rstn" LOC = "P174";
Actually, i Want to know what each pin # is for (The one mentioned in the Floor Planner of Project Navigator) ..is it for led ,Push Buttons etc
FPGA LABS
I AM CONDUCTING FPGA LABS AT A UNIVERSITY,CAN SOMEONE TELL ME WHAT SHOULD BE THE COURSE OUTLINE...??LIKE WHAT SHOULD WE MAKE , BCD COUNTERS ETC????ANY SUGGESTIONS????
All needed logical equations (equivalently, combinational circuits) can be constructed using the three logical operators (gates): and, or and not. Because of DeMorgan's laws, we only need either and and not, or (or and not) to form a complete logic. These same results can also be accomplished...
IN XILINX WE HAVE AND/OR PLANE NOT NAND/NOR.NAND /NOR ARE CALLED UNIVERSAL GATES,CAN BE USED TO IMPLEMENT ANY GATE,ALL LOGIC FAMILIES (MOSTLY) IMPLEMENT INVERTED LOGICS OR OUTPUTS.
BUT MY QUESTION IS CONSIDER I KNOW NOTHING EXCEPT THAT NAND/NOR ARE UNIVERSAL GATES,IF THEY ARE DECALRED AS SO THEN...
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