Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by navi_s

  1. N

    Analog Design Procedure

    Hello All, I have some general question about designing some Analog block and steps. Lets consider we want to design simple Current Source biased by simple PMOS current source with given GAIN, GBW, CL 1. First should be from given GBW and load capacitance obtain the Gm 2. Then we from given...
  2. N

    Cadence EDI example TCL script

    Hello, Can someone to share some example script for EDI. Thx
  3. N

    Choosing right W/L ratio

    Hello all, I'm novice in Analog circuit design, and I have one (could be a stupid question) So how to choose correct W/L ratio when design circuit? At example if the calculation says that we need ratio of W/L=2, how to take a decision for the ratio. Should it be, 4u/2u or 8u/4u and etc.? Thx
  4. N

    $fdisplay system task

    Hello, is it possible when using $fdisplay system task, to display the data also in simulation console? Thx
  5. N

    Continious and Discrete model difference

    Hello, I have an issue, trying to convert an S-transfer function to Z-domain. What the problem is: I'm using c2d Matlab function. When conversion is done i type "step" in command window to both transfer function and results are identical. But if I go to Simulink and draw both transfer function...
  6. N

    Transfer function implementation

    Hello, I have a question about transfer function implementation. So let suppose that we have designed some feedback system, which has been designed into S-domain. What are steps after, if we want to design a circuit based on this system function that we already have. Best regards
  7. N

    Metastability and simulation

    +nctfile+ thank you for your replay BR
  8. N

    Metastability and simulation

    nctfile So what is my idea. When simulation is run, and you have asynchronous process, veri often is happen that some setup or hold violation occurs. When it is happened, normally the Flip-Flop's goes to "X" state. And if "X" is propagated sometimes cause undesired circuit behavior. So the...
  9. N

    Metastability and simulation

    noiopath Hello, I have one question. How you simulate at example two asynchronous process, and how you avoid "X" propagation when metastability problem occurs? Thank you for your answers. BR
  10. N

    Represent 16 bit digits in Matlab

    matlab digits Thank you a lot
  11. N

    Represent 16 bit digits in Matlab

    how i can put 40000 to int16 Hello, Could some give me advice, how to represent 16-bit data in Matlab? Thank you in advance
  12. N

    How to begin SoC design about baseband processor for navigation communication?

    Re: SoC design Hello, here is some basic point to folow My advice is to start with basic function! 1. Firts - what this system must do. 2. Second - If you gonna to do some signal processing, type your algorithms 3. Make some block diagram of working algorithm 4. Retype your algrithms on CPU...
  13. N

    Question about FFT of a real signal

    Re: DSP and Real signal Yes, soryy.. So the question is: The FFT is correct for N*period of the input signals. What is the prosedure to get exactly a N*period of input signal, to make FFT.
  14. N

    Question about FFT of a real signal

    Hello, I have a question about FFT of real signal. If we have real signal, with unknown frequency, let suppouse the signal is in range in 20Hz to 20 KHz, and we must do FFT, but our FFT is limited to 1024 points of example. What is the trick of DSP in such signal. Best regrds
  15. N

    Gating clock problem_How to avoid glitch?

    Hello Here is verilog file with ClockMux implemented. //************************************************************ //Clock multiplexer //------------------------------------------------------------ // if SCK1 is high then clock output = CKO else output = CK1...

Part and Inventory Search

Back
Top