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If i understand your query correctly, u are using Synplify pro for doing the simulation and synthesis. If it is so u can directly take the netlist to VCS and do the post synthesis simulation. Hope this helps you..
ccs nldm
The basic difference between CCS and NLDM is :
NLDM uses a voltage source for driver modeling, where as a
CCS uses a current source for driver modeling.
The problem with NLDM modeling is that, when the drive resistance RD becomes much less than Znet(network load impedance), then...
Hi
If there are unused signals in the blocks which are declared in the interface, declare this signals as bit. These signals will be in the X state.
Hope this helps
Regards,
Naveen
Intrinsic delay is the delay internal to the gate(in other words gate delay). To be more clear, the time taken by the gate to produce a output after giving the input.
Fanout delay is the driving capability of the gate(the number of loads a gate can drive).
Regards,
Naveen
hai
This is the concept of named blocks in verilog
You can name a block and disable a named block
eg >> begin:write_op
write_op is the name given to this particular block
You can have any number of named blocks in your design with a unique name
Re: The difference between functional and gate-level verific
The same test bench will be used to verify the gate-level netllist
i.e put the gate level netlist and the same test bench used earlier for RTL code
low vt setup time
only setup time is used
because the max frequency is based not only on the flipflop characterstics but also on the combinational logic
Macros are intermediate cells
i.e they are not either the leaf level cells like AND, OR etc or top level cells like ALU, CPU etc
they are the intermediate cells combining of leaf level cells like mulitiplexers, decoders,encoders etc
The library containig the macro cell is called GTECH library
Re: mealy and moore?
The main difference of mealy and moore machines is determining the present state and next state
according to the requirement you choose either machines
Re: VHDL/Verilog
Verilog and VHDL are the two different hardware description languages used in the present day industry
Verilog is easy to learn for beginners but VHDL is much robust that verilog
both the languages have there own strengths and weakness
In Europe VHDL is used extensively and...
Re: Clock in testbench
hai
clock decleration with out initializing
always #25 clk=~clk
if you want to initialize , then
initial
begin
clk=0;
always #25 clk=~clk
end
The other way of declaration the clock
forever #25 clk=~clk
this is how we declare clock
bye
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