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make a new project and add all these relative .v files into the project, when you are testing the top module,it will automatically call all the submodules
Well,you say the written bit will not change even after power-down,that means to be an hard-ware change, only programmable device like EEPROM ，VHDL can't realise this function.
So i really advise you to look back in to your design to look for better ways to realize your design.
if you set an initial value to the register, and that value keeps unchange at all, maybe the optimization step will connect it to VDD or VSS. Or why don't you connect it to VDD or VSS directly?Register can be saved.
when you define that network as clock, i think DC regard it as ideal_network by default,so it will no add buffer tree to that network,and if this clock will drive lots of registers, it needs large gates.
i think the delay will be reduced after P&R.If you do want to see the result after DC，you...
maybe you can try "set_ideal_network [get_clocks all_clocks]"
actually, when the network is defined as clock, it is regared as ideal_network,and don't touch it during DC synthsize.
Hi,
If your circuit is on P-sub,then all the substrate port of NMOS should be connected to GND to decrease the bias current between P-sub and N-Well,and since Pmos is set in N-well,mostly the substrate port can connected to Vdd,and the can also be connected to source of PMOS to eliminate the...
Hi,prcken
I think when Vin is high enough to reach Vdd,M1 is triode,and the Drain voltage of M1 is about the value of the drain voltage of vss(mostly a biased NMOS),then,node X is pull down,and the current cross M5 increases,which result in the increase of the Voltage of the Drain of M5,so the...
n-FET means N type field effect transistor,Q1,Q2 are symbol of a n-FET
Users get the logical of the device and the company who yield the circuit have the internal circuit of it.
Post a circuit as a example:
As is know that the ro can be get from vo/io.
I can get vo,in AC analysis.and the ac current of M35 and M36.But i don't know how to get ro.
Because i still cant get the ac current inflow to the output,for the direction of AC current is unkonw.
So i want to know...
Hi goldsmith,
It's so kind of you to reply me.
And I think i have find the answer of the problem.
Because i have carelessly set the Frequence of the input too High,so the AC output would surely be lowered.
And more importantly,I set the DC voltage of input to 0V,which should be 0.9V as a circuit...
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