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Hi everone
i am facing DRC errors such as ESD.10g in cadence layout using 0.18um tsmc library. how to address this error. i have attached the image for reference.
Dear, I am working on a layout of capacitor-based circuit. i have passed all LVs and DRC, but i have one error in ERC, as shown in the figure. This error shows that ntap is connected to GROUND. Could you suggest mehow to address this problem. i have crossed checked multple times my circuit it...
thank you dear for your response. I got your point and changed the output RC value as per the requirement to pass the 50MHz modulated output. however still ac input signal has no impact on the output as I have changed the value of the AC input components also. could you guide what is wrong with...
I am using 50 MHz as a carrier signal and a pulse signal as the data signal. Unfortunately, I could not get my desired modulated ASK signal. I am using ADS software. Kindly guide me on how to do it. You can share related materials or papers. I have attached the modulated output with the pulse...
These days I'm trying to find a way to simulate the transient performance of on-off keying (ASK) in ADS, but I didn't figure out how to build the such model. An on-off keying modulation should contain several transistors and passive components. I am looking for a model or circuit containing...
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