Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hereby the schematic of our circuit. The +5V are already changed to +Vin, because this was giving a problem.
The capacitorbank was fully discharged to 45 mV.
Reducing the Cap bank isn't a possible.
We are simulating the circuit atm. We'll post once we're done with simulating.
Hey
I use a LTC 4211 to limit the inrush-current of a capacitorbank. The first problem was that we pulled the FAULT and RESET pin to 5V after the FET (so at start the pins aren't pulled up). We solved this issue by connecting those pull-up resistors to VCC.
Hereafter the LTC starts conducting...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.