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Recent content by Nandini Ganig

  1. N

    FPGA design ( voltage related)

    Can we use 1.8 regulator to drive 3.3 input pin Thanks in advance, Nandini
  2. N

    FPGA design ( voltage related)

    Hi all, Can we drive the input pins above the supply level of the VCCIO regulator? Thanks in advance, Nandini
  3. N

    checksum calculation in ip

    I am implementing IPv6, communicating from pc to fpga I know how to calculated checksum but the problem lies where i am seeing the capture protocol in Wireshark , there the checksum is zero but when i am seeing in logic analyzer the checksum is correct ( some number other than zero) can anyone...
  4. N

    crc 32 ethernet-magic number

    Hi all, I am implementing ipv4 from pc to fpga, i am getting the crc32 properly and i am even able to capture it in wireshark tool. But I am not get the theoretical concept behind the magic number(0xC704DD7B) and how it is produce. Please anyone can help me. Thanks in advance. Ganig
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