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Recent content by Nanda_DFT

  1. N

    How hold violation caused by below mentioned Scenceio

    1. Have you simulation run considering min corner or max corner SDFs? 2. Do you see the failures or mismatches during 0-delay sim on the same register you are talking about?
  2. N

    Test-per-scan v/s Test-per-clock

    What is the difference between the terms Test-per-Scan and Test-per-Clock?
  3. N

    LBIST architecture - Industry standards

    Latest LBIST architecture is in use as per current industry trend? Theoretically it is mentioned STUMPS as industry architecture.
  4. N

    On-Chip Clock logic (macros) placement during Testability insertion

    Is on-chip test clock domain logic (macros) placed before clock domain root or after clock domain root?
  5. N

    DFT Scan chain blocking detection

    How to detect scan chain blocking in scan inserted netlist if SPF file is detected to have scan chain block condition.. Does this scenario concern the Physical Design implementation?
  6. N

    [SOLVED] Clock domain crossing problem in DFT

    Thank you for providing me the hint.. :thumbsup:
  7. N

    [SOLVED] Clock domain crossing problem in DFT

    How to avoid bit getting launched in 1 clock domain and getting captured in another clock domain? needed theoretical concept
  8. N

    What is Tranisition Delay and Path Delay Fault models in DFT ATPG?

    Can I get the difference between TDF and PDF models in DFT ATPG
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