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Hello Sir/Madam,
I have a verilog file, I have to find the power dissipation of the circuit at gate level. Can anyone suggest me which software is helpful in finding the power dissipation of the circuit at gate level. Please give me the details how i can use that software to find power...
Hello,
how can i convert a verilog file into spice netlist format. I have CADENCE software, I tried to import verilog file and export in spice netlist form, but I am facing some difficulties. Can you suggest me any other method.
yaaaaaaaaaaaaaa thanq very very much.....the information u hav given is very useful & if u dont mind can u giv me ur mail id......so dat if i get any doubts i may mail it to u
hiiiiiiii....i am new to prime time......i need to calculate the power & delay of the logic circuit which i hav....i hav simulated it in xilinx....the vhdl code is working properly bt we cant find power dissipation in xilinx na dats y i am gng for primetime tool for finding dem.......can anybody...
sorry sir......the link u sent is unable to get connected.......it is dispalying as page is not found
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i hav simulated my code using test bench & it is working properly and i am getting the correct outputs......now...
thank u sirrrrrrrrrr. the information which u hav given is helpful.what is the next step i hav to do after having my vhdl code. whether there is any different coding style for prime time or can it be generated from the vhdl code itself.....pls give me commands if so......plsss plsss sir its...
plss can anybody send me the free download link of power compiler or any other tool which calculates the power at gate level design....thanks a lot & a lot......thanks thanksssssss...i wil be thankful to all of u....pls plsssss
plss can anybody send me the free download link of power compiler or any other tool which calculates the power at gate level design....thanks a lot & a lot......thanks thanksssssss...i wil be thankful to all of u....pls plsssss
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