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Hi,
My comments were about transient simulations. If you need to find SNR through equations, you may replace Z (or S) with exp[jw] (or jw), where w=2*pi*f. Then sweep the f along with the bandwidth and calculate the signal and noise power.
Ali
Could you explain more on the aliasing phenomena of a clocked DAC?
My understanding is that such aliasing could occur in a clocked ADC when the input bandwidth is higher than clock frequency (fs). Then the noise distributed over the input band is folded between DC to fs/2.
In a clocked DAC, its...
In a delta sigma modulator, it is well-known that only DAC and the first integrator can contribute to the output noise. It can also be tested by behavioral simulators such as Matlab and verilog-A.
I found that transient noise analysis is not match with noise analysis. An experienced designer...
Can the maximum step size in a transient simulation effect on the amount of injected noise?
fs=5.12 MHz,
tran tran stop=52m errpreset=conservative noiseseed=1 noisefmax=fs noiseupdate=step \
maxstep=1n write="spectre.ic" writefinal="spectre.fc" annotate=status maxiters=5
Please find the enclose figures showing structure of the delta sigma modulator, test setup for the integrator, and some results for the integrator.
In the modulator only the integrator is circuit and the rest are verilog-A models.
The integrator shows input-referred noise of -147 dB, and...
To calculate SNR more calculations than a simple FFT are required. So, it is easier to import the results into matlab, then calculate the SNR.
In order to transfer results to Matlab, one can write a Verilog-A module to capture the output of the modulator in right time based on modulator clock...
Hello all,
I have a continuous time (CT) third order delta sigma modulator that produces SNR=98dB when the circuit noise (thermal and flicker noise) is not considered in a transient simulation. When I use transient analysis with transient noise in Cadence-spectre, the SNR drops to 60dB...
Hello all,
What can limit the input signal level for a delta sigma modulator?
I used an example given in the delta-sigma toolbox from Matlab and optimized a 3rd-order NTF for:
-Continuous-time with RZ DAC
-all poles at DC.
-out-of-band noise Hinf=1.7
-BW = 20kHz
-OSR = 128...
Dear all,
In my design, total power consumption estimated after synthesis by Cadence-BuildGates is:
Internal Cell + Leakage + Net =
0.2904 + 3.9775 + 0.3833 = 4.6512 mW
While, after place-and-route, Cadence-Encounter reports:
Total leakage power = 337395.002511uW
Can anyone tell me why...
multiple set_operating_conditions
Hi Avimit,
If I use "set_operating_conditions", then I have to set both bc and wc libs in the "target_library" already. In this case, DC uses the bc lib for synthesis, which is not desired.
If "target_library" is set only by wc lib, then I cannot use...
multiple target library in design compiler
Hello all,
In Design Compiler, when I use "set_operating_conditions" with wc and bc libs, then "report_design" shows:
Library(s) Used:
CORE90GPLVT (File: ./SYNOPSYS/PR/CORE90GPLVT/LM/CORE90GPLVT_bc_1.10V_m40C.db)
CORX90GPLVT (File...
hello all,
i am using Cadence BuildGates tool to synthesis rtl for cmos90nm STM technology. The logic is as big as half a million gates. My issue is the BuildGates stops working after a few hours try with following error:
INTERNAL_ERROR: (mem_enomem2_from) - no memory available for...
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