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Recent content by naalald

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    Need a Paper: Electronic Circuit Diagnosis with No Data

    Hello, I need this paper: https://ieeexplore.ieee.org/document/8819424 Thanks.
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    ABB RTU Internal Protocol

    Hello, Does anybody know about the internal protocol of ABB RTU560? In one of its documents, it says the internal communication of the RTU is based on IEC-101. But, when I get some data from the serial port (TL3695) of one of the cards, it does not look like 101. Thank you.
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    [moved] 74HC4060 Oscillator/Counter Frequeny Problem

    Hello, I have an oscillator/counter (74HC4060) which is part of a 100%-properly-working board. The oscillator with the external resistors and capacitors, generates a 73.5 kHz pulse (pin # 9, which is CTC). I'm trying to copy this oscillator in another board and I'm using the exact R & C values...
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    [51] SRAM WR pin is not anabled

    Thanks Klaus, Hardware I'm pretty sure about wiring, cuz at the startup the SRAM WR pin gets a few enable pulses but after that I don't see anything. About the software: I have a FLASH which has the program on it cuz 80c32 is ROMless. At the startup some instructions are loaded from FLASH to...
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    [51] SRAM WR pin is not anabled

    Hello, I'm working with 80c32 micro and I have a AM29F010 Flash and a HM6264 SRAM. I have this problem that when I turn on the circuit, the SRAM WR pin which comes from micro WR pin, is not enabled at all. What is the problem? Thank you.
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    Using CapTab for capacitance calculation

    Thanks for the information, I'm using this but I'm not able to translate the table, like for example for one transistor there are 7 nodes! And those are like this: T1:int_SI T1:int_GP T1:int_DI T1:int_BS T1:int_BP T1:int_BI T1:int_BD Does anybody know what these are? Thanks.
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    Error running post layout simulation

    Hi, I'm running post layout simulation with cadence and I'm getting this error: ERROR (SFE-23): "input.scs" 63: re1 is an instance of an unidentified model M2. I tried in two ways: First, I ran QRC for R and C and, second I ran just for C. The first time I got this error but the second time no...
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    The relation between an ADC's Sample-rate, Bandwidth and it's S/H Speed

    When they say, for example, a 125 MSps ADC with 2.2 GHz analog bandwidth: 1- This is called undersampling (or sometimes IF sampling), right? 2- What should the speed (the maximum clock frequency) of the input S/H be?
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    Designing an Opamp for 4 GHz

    Designing an Opamp with 4 GHz BW I'm designing an opamp and need 78 dB gain and 4 GHz BW with 3.5 pF Cload and 2.5 V supply voltage. I can get the gain with a single stage folded-cascode opamp, but the best result for the BW is just 1.8 GHz. Would you please let me know your opinion about this...
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    Noise in Time Interleaved and Double Sampling Circuits

    Suppose we have a time interleaved system (e.g. ADC) with two channels, which means the input samples are used by each channel every other one. What would the total noise of the system be? Is it going to be the sum of the noises of the channels or not? The same question arises in double sampling...
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    A Question About Delta Sigma Modulators

    I'm designing a 2nd order delta sigma ADC. I want to compare the systematic results with circuit design. In Matlab I have a 73 dB SNDR but in HSpice (all blocks are ideal) I have 66 dB SNDR. I don't know why? What could be the reason?
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    Difference Between Offset and Resolution in a Comparator

    resolution of a comparator What is the difference between the offset and the resolution in a comparator?
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    A Question About Delta Sigma Modulators

    The OTA works in all corners well enough.
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    A Question About Delta Sigma Modulators

    Of course not. The nominal voltage in 0.18 um is 1.8 V. In fact, my design is considered a low voltage design.
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    A Question About Delta Sigma Modulators

    Hi, Thanks for your reply. The details are so: SC architecture, 1 bit quantizer, No parasitics are considered, process is 0.18 um and the supply voltage is 0.9 V. Thanks for your suggestions.

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