Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Does anybody know about the internal protocol of ABB RTU560? In one of its documents, it says the internal communication of the RTU is based on IEC-101. But, when I get some data from the serial port (TL3695) of one of the cards, it does not look like 101.
I have an oscillator/counter (74HC4060) which is part of a 100%-properly-working board. The oscillator with the external resistors and capacitors, generates a 73.5 kHz pulse (pin # 9, which is CTC). I'm trying to copy this oscillator in another board and I'm using the exact R & C values...
Hardware I'm pretty sure about wiring, cuz at the startup the SRAM WR pin gets a few enable pulses but after that I don't see anything.
About the software: I have a FLASH which has the program on it cuz 80c32 is ROMless. At the startup some instructions are loaded from FLASH to...
I'm working with 80c32 micro and I have a AM29F010 Flash and a HM6264 SRAM. I have this problem that when I turn on the circuit, the SRAM WR pin which comes from micro WR pin, is not enabled at all.
What is the problem?
Thanks for the information,
I'm using this but I'm not able to translate the table, like for example for one transistor there are 7 nodes! And those are like this:
Does anybody know what these are?
I'm running post layout simulation with cadence and I'm getting this error:
ERROR (SFE-23): "input.scs" 63: re1 is an instance of an unidentified model M2.
I tried in two ways: First, I ran QRC for R and C and, second I ran just for C. The first time I got this error but the second time no...
When they say, for example, a 125 MSps ADC with 2.2 GHz analog bandwidth:
1- This is called undersampling (or sometimes IF sampling), right?
2- What should the speed (the maximum clock frequency) of the input S/H be?
Designing an Opamp with 4 GHz BW
I'm designing an opamp and need 78 dB gain and 4 GHz BW with 3.5 pF Cload and 2.5 V supply voltage. I can get the gain with a single stage folded-cascode opamp, but the best result for the BW is just 1.8 GHz. Would you please let me know your opinion about this...
Suppose we have a time interleaved system (e.g. ADC) with two channels, which means the input samples are used by each channel every other one. What would the total noise of the system be? Is it going to be the sum of the noises of the channels or not?
The same question arises in double sampling...
I'm designing a 2nd order delta sigma ADC. I want to compare the systematic results with circuit design. In Matlab I have a 73 dB SNDR but in HSpice (all blocks are ideal) I have 66 dB SNDR. I don't know why? What could be the reason?