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Recent content by mvvijay78

  1. M

    Decap cell Estimation.

    how leakage in decap I believe you first need to do a dynamic IR drop analysis to come up with the estimate of the amount of decaps required and the area where they are required. In the process above 130nm actually lot of people just go ahead and add decaps similiar to fillers without actually...
  2. M

    Signalstorm to ETS migration

    signal storm cadence I would like to know if there is any migration document to move from the Cadence signalStorm to Cadence ETS. We are currently using the signalStorm as delay calculator in the signoff flow and now this signalstorm is part of ETS. Has anyone does such transition . The...
  3. M

    Power pads in TSMC library

    tsmc pad library Hi, I am using magma blast fusion.Any idea how to do it in this tool. Regards Vicky
  4. M

    Power pads in TSMC library

    io pad lvs Hi, I would like to know how to use the PVDD1SDG and PVDD2SDG power pads in the TSMC pad library.It is given that the VDD1 pad is to be used for Core voltage and the VDD2 pad is to be used for IO voltage.But each of these pads have VDD: ,VSS: ,VSSPST: ,VD33 pins.How to connect the...
  5. M

    difference between feeder cell and filler cell

    Hi, Under the pad library fromTSMC we have 9 feeder cells.Are they same as filler cells.I am asking this question as in magma tool we have toput a propery called model_type on each cell and only pad_filler is available nothing like feeder is available. Regards Vicky
  6. M

    sdf v/s spef file in magma

    spef file and sdf Hi, I would like to know when we write out a sdf file after routing is it the case that the delay values reported for each net is based on the R and C's present across those nets. To reframe the question i would like to know how different will be the delay values reported by...
  7. M

    Comparision between DAA and SLIC

    slic daa Hi Can any one explain the difference between SLIC and DAA? Regards Vicky
  8. M

    Manufacturing grid size of 0.18u technology

    Re: Manufacturing grid size Hi, It is 5nm. Regards Vicky
  9. M

    orphan nets in the imported GDSII

    Hi, I have a peculiar problem related to generation of GDSII in balst fusion.After completing a block we exported the GDSII for the same.When we import back the same GDSII into the tool we find that there are many nets which are named as orphans.Why is this happening.Have any one come across...
  10. M

    Lef v/s GDSII import for a hard macro

    Hi, If for a hard macro both LEF and GDSii views are available it is normally recommended that we import the LEF view .I have following questions 1) Is there any difference between LEF and GDSII apart from one is text file and other is an binary. 2) If we import the LEF file and continue our...
  11. M

    Does TSMC offer any tools like chip sizer

    Hi, Any idea if TSMC offers any tools similiar to UMC's chip sizer which helps in eztimating die size based on FAB data? Vicky
  12. M

    checklist to be followed for netlist handover from front end

    Hi, Can anyone one give the checklist to be followed when a netlist transfer happens from front end to backend for the physical design in ASIC? Vicky
  13. M

    io limited v/s core limited design

    is design io limited? Hi, I would like to know how to identify if a design is IO limited or core limited.Once decided what is the methodology to be followed to hand;e each one of them? Regards Vicky
  14. M

    How to build a PSPICE library for an opamp ?

    Re: PSPICE help Hi, Did u try the model editor in pspice?That can be a very good starting point to start modelling. Vicky
  15. M

    Is it required to generate SDF file in magma???

    Hi, Magma has inbuilt sta timing engine.Is it required to generate sdf file even in this flow.What is the difference in timing analysis done using sdf file and using the built in timer ? Vicky

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