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Hi,
Good question. As said earlier, the main intention for hold violation check is to ensure that the flop always gets the value that was on "D" pin before. If the clock delay between the launch flop and the capture flop is more than that of the data path, then it results in hold violation and...
Hi,
I think, it is both ways. Designers first do the transistor level simulations of their libraries and then compare it with test-chip results to factor in some variation and other stuff.
So, I think to answer your question, it is both.
HTH,
-Tejas
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