Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by mvj

  1. M

    How to add phase noise to clock and obtain time domain sampled sequence of the same?

    Hi, I have phase noise numbers of a clock signal. e.g. PLL_freqOffset = [1e3 10e3 100e3 500e3 1e6 10e6];#[Hz] offset freq. from VCO freq. PLL_PNdata = [-40 -45 -50 -55 -60 -120];%phase noise [dBc/Hz] I would like to add this a 100MHz sine wave clock source: Fs = 1e9...
    • mvj
    • Thread
    • Replies: 0
    • Forum: MATLAB
  2. M

    LC VCO with Capacitor filter, what is the cap doing?

    Thank you for the explanation!! Can you please mention any papers that talk about this. May I know why/how phase noise improvement happens only for a small range of capacitor values; above and below this cap range the phase noise degrades. Thank you!!
  3. M

    LC VCO with Capacitor filter, what is the cap doing?

    Thank you for your inputs!! I have actually removed some of the circuitry in an attempt to keep it simple and not over crowd it. There is actually 1. Bandgap voltage reference generator providing reference to a 2. voltage regulator with about 20pF on chip output capacitor (no off chip...
  4. M

    LC VCO with Capacitor filter, what is the cap doing?

    Hi, The circuit in the picture is a complementary (NMOS & PMOS) Negative resistance core of an LC VCO. L, C and varactor are OFF-CHIP components connected across pins (IP,IP1B) and (IP1,IPB). The supply is a regulator output VREG and current in the oscillator is determined by resistors...
  5. M

    [Moved]: Div 2/3 prescaler with 50% duty cycle

    Hi Klaus, Thank you for your suggestions and regarding.. After 10 input clock cycles, in the 11th clock cycle would it be possible to use the falling edge of the input clock to make the output clock go low, in this way..the output clock signal will have 50% duty cycle.. Please suggest...
  6. M

    [Moved]: Div 2/3 prescaler with 50% duty cycle

    Hi All, Please find below more information regarding the same as asked.. There is a PLL, its output clock is divided down by an "OUTPUT DIVIDER"and used as clock for an application(s). Now, the application uses both rising and falling edges of the clock it is provided with and the clock needs...
  7. M

    [Moved]: Div 2/3 prescaler with 50% duty cycle

    Hi All, Well..actually I did not make myself clear..sorry.. I need the 2/3 prescaler to use it as part of the DIVIDER that divides the PLL output to generate the required output clock frequency. Based upon the output frequency required I will change the division ration of the divider. A multi...
  8. M

    [Moved]: Div 2/3 prescaler with 50% duty cycle

    Thank you Erikl, I have been looking around and already went through link you gave..unfortunately the duty cycle is not 50% in any of the ideas presented..So, I was wondering if there is a way to do it.. Thank you, mvj
  9. M

    [Moved]: Div 2/3 prescaler with 50% duty cycle

    Hi, I need to design a DIVIDE 2/3 prescaler (as part of the DIVN multi modulus divider in a PLL) with 50% duty cycle. I am aware of the usual designs in which one of the pulses is swallowed, the output of the divider does not have 50% duty cycle. Any suggestions on this please. Thank you, mvj
  10. M

    LC VCO negative resistance design

    Hi, Can you please provide information on designing the cross coupled negative resistance block of an LC VCO. How to decide W and L values - what are the things to keep in mind, trade offs etc. Any references to papers are also ok. Thank you, mvj
  11. M

    [SOLVED] Cadence Spectre Transient simulation failure

    Hi, I ama getting this error message while running transient sim. Error found by spectre at time = 1.93594 us during transient analysis `tran'. ERROR (SPECTRE-16929): Transient analysis is simulating with step size less than 2 as for 1000 steps. Change option...
  12. M

    UpConversion Mixer Noise

    Thank you biff44!! The noise from 0.980 to 0.990 GHz does not overlap with the noise in the upconverted signal (i.e. 1.010 to 1.020 GHz) and it will both up and down converted to frequencies different from (1.010 to 1.1020 GHz). So can we say that in a mixer output, the upconverted signal has...
  13. M

    UpConversion Mixer Noise

    Hi, In the case of a down conversion mixer, the noise from both the RF and image frequencies are down converted. This means that there is twice the noise power in the down converted signal. May I know what is the situation in case of up conversion? Does it have up converted noise only from the...
  14. M

    Verilog A modelling of a current mirror (voltage controlled current source)

    Hi, I am trying to write a verilog A model for Voltage controlled current source. module VCCS(p,n,pc,nc); inout p,n; input pc,nc; electrical p,n,pc,nc; parameter real gain=1; branch (p,n) iSrc; analog begin I(iSrc) <+ gain*V(pc,nc); end endmodule It works fine when there is a load...
  15. M

    Background/foreground colour of Cadence Spector log file

    Hi, May i know how to change Background/foreground colour of Cadence Spector log file. Thank you, mvj
See more

Part and Inventory Search

Back
Top