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thank you for your reply , I will ask my colleagues about it , however in case there are no verilog modules available for the standard cells then how can I get it ? is there any other option?
thank you soo much
hello everyone
please , kindly help me
I finished writing my design using verilog, functional simulation by modelsim is working well. then I synthesized my design by using ( Encounter(R) RTL Compiler RC10.1.306 ) to create the netlist and SDF (standard delay format) files successfully . I used...
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