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Recent content by Musawir

  1. M

    DDR4 SDRAM

    @dpaul Please comment on this.
  2. M

    DDR4 SDRAM

    Do we need DDR PHY Interface between Memory Controller and DDR DRAM Memory?
  3. M

    DDR4 SDRAM

    Thanks for your kind response. As I am new to DDR. Now I am just following the DDR4 standard JEDEC spec. I want to implement the whole system as in the above figure. Is it possible first design a memory module and then the memory controller?
  4. M

    DDR4 SDRAM

    I am going to design DDR4 SDRAM in verilog. So the below figure shows the memory subsystem as DDR controller, DDR PHY and DDR DRAM. I have to design all of these subsystem? From where I will start? Please alse refer me some good materials related to DDR4 SDRAM. Thanks
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