Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
thanx for da reply...
actually i m comparing the power and delay of 2 techniques,for dis reason i want to keep vth low with respective supply voltage,but vth is increasing as decreases the suply voltage,for dis i want to know,wat to do to decrease the vth.
thanx once again.
hi to every1,
Actually i m working on cadence virtuoso....
i want to know how to decrese threshold voltage with respective to supply voltage....
i want to decrease the vth with decreasing vdc...
please help me to do dis.
thanx in advance
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
