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hi..
i am layouting full adder using cmos in cadence virtuoso,but i m facing problem while connecting bulks to the supplies...
anyone tell how to connect these to supplies...
i have attached a fig. of my layout..
help me out.
regards.
hi all..
I am doing layout in cadence virtuoso tool.
When i run ASSURA DRC(Design rule checking) to debug the errors its showing one
error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um.
Its indicating at every NMOS in the design.
I am unable to clear this...
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