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Recent content by muhammadali201

  1. M

    Synthesize sram using Synopsys Design Compiler

    Thanks a lot guys...All problems Solved. Regards,
  2. M

    Synthesize sram using Synopsys Design Compiler

    Thnks Hairo, I now have Synopsys compatible .lib files generated by ARM Memory compiler. However, to instantiate the design in my RTL, do I also have to generate verilog file?. Is there any info in .lib files that tell me the exact port list and dimensions?. At the moment, I only know the...
  3. M

    Synthesize sram using Synopsys Design Compiler

    Thanks a lot Hairo, However, I don't have any .db file for memory. Memory-Compiler generated .dat files (FE views). Do I just change the extension or use the dat file as it is?
  4. M

    Synthesize sram using Synopsys Design Compiler

    I have FE Files generated from ARM Memory Compiler. These are couple of files with .dat extention. Now I am confused about how to use them in Synopsys Design Compiler for synthesis. I have top level verilog RTL in which I have instantiated 8kx4 RAM. For this 8Kx4 RAM, I want to use the memory...
  5. M

    Need Help In identifying Russian IC OC175YB4.

    I have a design with Russian IC OC175YB4. and I am unable to identify this part. It is connected with Clock crystal so I am guessing it has something to do with clock. I'll really appreciate any help in this problem.
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