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Recent content by muffassir

  1. M

    How to do trans analysis for these exp?

    Hi all, In my circuit for multiplier i have 2 inputs Ix and Iw For DC i have used these expressions. Ix+=(1+x)/250n Ix-=(1-y)/250n Iw+=(1+w)/250n Iw-=(1-w)/250n Now i want to do the transient analysis :::As given in IEEE paper tht i am using For 100Hz with peak value-40nA(x=0.16) For 4KHz...
  2. M

    [SOLVED] How to get Iout/Ib in the Y-aixs in DC analysis

    Hi all My output current is Iout ...and i have some fixed bias current Ib=250nA, During DC Analysis i am varying one of the design variables so that will appear of x axis. ON Y-Axis i want Iout/Ib i.e. the current will be normalized to -1 and 1. How to do that in CADENCE 6.1.4...here am...
  3. M

    Ipulse wave in Cadence

    Hi all, I am using Cadence 6.1.4 I want to have the pulse waveform that will start from 0A for 10ns and then rise to 15nA and stay for next 20ns. When i am filling the option of ipulse instance : period= 30ns, pulsewidth=10ns. what i get is the waveform that is ON for 10ns and OFF for next...
  4. M

    Error in DRC in cadence

    Hi all, I am getting an error in my layout while running the DRC . The error is PSUB_StampErrorFloat I dont have any NMOS devices in my circuit layout. revert me back at the earliest. \
  5. M

    how to size transistors in inverters for a particular load

    Hi Vishwanathan, Here is below attached pdf for the derivation u can refer... Actually what is given in the first pdf (see my first reply) the Inversion coefficient (IC)is for the EKV model of the MOS i.e. this model is valid in all regions of operaion of the MOS. IC= Id/(Io (W/L))...
  6. M

    matching in ic layout design

    read the book Hastings, Alan. The Art of Analog Layout. New Jersey: Prentice Hall, 2001. This is good one !!
  7. M

    how to convert the Spectre results into .ps or .pdf format

    Hi faiq Khalid, I was also facing same problem.I suggest you to create service request in the online support of CADENCE. You need to do some changes in the .cdsplotinit file to be able to get the plotter name and size of A4. Then i am sure you can print it to .ps file hope this helps you .
  8. M

    cmos fabrication

    becoz most technologies being used in market are based on p substrate technology!!see TSMC etc there are some n substrate techonologies present ...do some googling!
  9. M

    how to size transistors in inverters for a particular load

    hi Vishwanath , vt means thermal voltage approx equal to 0.026V
  10. M

    how to size transistors in inverters for a particular load

    hi vishwanath, you need to first determine what specific current you want in the inverter MOS. You can refer the pdf i am attaching here for refrence.. no matter wht model u are using for the simulations atleast this method will help u arrive at the near conclusion .
  11. M

    [SOLVED] How to determine the Specific current of the MOS transistors in CADENCE

    can anyone send me the spreadsheets of the author BINKLEY....I cannot download them from this page: **broken link removed** It gives me erorr when i fill all fields and click submit !!. Please download a set and then email me at muffassir@gmail.com Or else if u own it then pass it to me ...
  12. M

    [SOLVED] How to determine the Specific current of the MOS transistors in CADENCE

    Hi Erikl Sir, wow thts the book i needed the most..!!! I got it from one of my sources and reading started also.... Thanks a lot for unconditional replies to the Posts...may *** keep you Long Live !! Bye Tc.
  13. M

    [SOLVED] How to determine the Specific current of the MOS transistors in CADENCE

    Hi all, How to determine the specific current of the nMOS /PMOS transistors. Specific current is given by Is=2nuCoxVt(square)W/L which is used in the Ids equations of the MOS in strong and weak inversions. I want to know the procedure to find the specific current in CADENCE VIRTUOSO 6.1.4...
  14. M

    is it possible in cadence trans analysis

    Hi Keith, Thanks a lot for the help .I got the expected waveforms.The only thing i did is ... In the capacitors properties there is an field for Initial condition i set it to '0' . That did the job !!! Regards, Muffassir
  15. M

    is it possible in cadence trans analysis

    Thanks Keith, I simulated the circuit using Vdd as vpulse(V1=0,V2=3.3, Period=120us, Delay=200ns, tr=tf=1u, Pulsewidth=75us) Vin as triangular wave ( V1=0,V2=3.3, Period=100us, Delay=200ns, tr=tf=50us, Pulsewidth=0) Vc as Pulse( V1=0,V2=2V, Period=100us, Delay=500ns, tr=tf=2u...
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