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thank you for the explanation. I was thinking on the point that there must be solution to such situations where for an input bit 0 instantiation of B1 and for input bit 1 instantiation of B2 take place. such kind of scenarios are very common. how can we deal these in verilog.
dear all
is there any way to instantiate procedural block using case/ if-else statement? if not is there any alternative? i am using verilog on xilinx platform for code. for example :
if
synthesize this procedural block
else
synthesize this procedural block
etc.
or a more...
Dear all
How can i remove the following error.
"sel is not a constant"
case (sel)
1'b0:
always @ ()
begin
-------------------
----------------
end
1'b1:
always @ ()
-----------------------
---------
end
endcase
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