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Recent content by mta97e

  1. M

    only work frist time simulation, doesnt work for subsequent

    I have this very simple FIFO and is part of the lager design, the signals InA_i[8:0] and InB_i[8:0] are not connected to anywhere to isolate them from the design. I isolated them for debugging purpose. The problem is, I simulate the code in modelsim. First time I load the design everything...
  2. M

    Xilinx FPGA development board

    Is any Xilinx FPGA development board out there with onboard PowerPC. Not the powerpc inside FX or v2 pro series.
  3. M

    Can't see the clock using ILA of chipscope

    Re: chipscope doubt u r sampling the signals in chipscope using ur clock, so u wont be able to see the clock in chipscope
  4. M

    Xilinx ISE and multiprocessor

    I am using windows XP and dual core, dual xeon processor and it uses only one processor. my queation is Does xilinx ISE run on multi processor? and if how do it do it? thanks in advance.
  5. M

    speed of computer components

    i m not sure PCI works at 100 and 133 .. PCIX works at 100 and 133
  6. M

    speed of computer components

    no no no no.. u r not confuse about PCI.. you dont know about PCI.. yes PCI works at 33Mhz, it also works at 66MHz
  7. M

    what is the difference between Vertex and spartan from xlinx

    difference between spartan fpga and virtex no spartan cannot do everything what virtex can do... , forget about mil, or commerical..
  8. M

    what is the difference between Vertex and spartan from xlinx

    vertex fpga family difference ok... the difference is the virtex can do waht spartan cant do... some of the things can only be done on virtex.. not on the spartan
  9. M

    Which signals should be included in the process sensitivity list ?

    Re: Sensitivity list thanks for pointing my mistake... I remember, during my University days(2002), we were taught that sensitivity list governs the synthesized circuit. It doesnt seems to apply anymore now. Is it becasue the synthesis tools become smarter? Or the text book was wrong...
  10. M

    what is the difference between Vertex and spartan from xlinx

    sparten & vertex i think.. start up sequence is different
  11. M

    Which signals should be included in the process sensitivity list ?

    Re: Sensitivity list clkDiv shouldnt be in the sensitivity list. I do not agree with it. In this particular case, there is no harm by putting clkDiv in the sensitivity. But sensitivity list governs the output of the synthesis and it could leads to disastrous sitiuations if we dont define the...
  12. M

    how to bidirectional signal in xilinx EDK tool ???

    iobuf xilinx I am not sure how you define the INOUT in yout wrapper. inout_i: IOBUF port map ( O => out, IO => inout , I => in, T => t ); post ur top level file here?
  13. M

    How to calculate throughput and bandwidth requirement for each transfer in USB ?

    Re: Throuput of USB https://www.usb.org/developers/docs/ check the link, you can download the specification USB Data Transfer Types The USB specification provides for the following data transfer types: Control Transfer Control Transfer is mainly intended to support configuration...
  14. M

    How to start up the XUP Virtex-II PRO board?

    virtex 2 pro tutorial you get the platform studio. And create a system for custom board. The process is pretty much straight forward, you add the FPGA, GPIOs, DDR, ethernet, SDRAM, UART ... just follow the instructions and add the components on ur XUP board... da..da...da...da..... that is...
  15. M

    Typical IC Design interview questions

    Re: IC Design Interview rule of 3
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