Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: Verilog coding query
Did you consider something like:
reg [9:0] max;
...
max<= (c1>c2&&c1>c3&&c1>c4&&c1>c5)?c1
:(c2>c3&&c2>c4&&c2>c5)?c2
:(c3>c4&&c3>c5)?c3
:c4>c5?c4
:c5;
Might be a lot to get done in one clock. What is you clk freq...
sr flip flop vhdl
S R and CLK?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FDRS is
port(
Q : out std_ulogic;
C : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic;
Clear: in std_ulogic
);
end FDRS;
architecture FDRS_arch of FDRS is
begin...
I need to see more detail of the file and more lines, but it looks like something you could make short work of with a pearl script. (or python script) I have never seen an image converter specifically for something like this.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
