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Dear all. In my process (0.6u 25HV option) I use nmos Cap. By simulation (Cadance) I have 5% accuracy. In SPICE distortion of Tox by corners arround 4%. In reality on wafer will I have this accuracy or not?
Sambody have experience in it?
P.S. I use HV NMOS CAP (Tox=690 +/-30A)
TNX beforehand.
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