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Recent content by msdarvishi

  1. M

    Unable to allocate all 2GB of DDR4_PL in ZCU106

    Dear all, I have a block design targeting a ZCU106 board. I have used the Zynq UltraScale+ MPSoC to realize the Processing System and XDMA Bridge to PCI Express to implement PCIe. I put a DDR4 SDRAM in the block design which is the DDR4_PL and I would like to allocate 2GB of memory to it. But...
  2. M

    What does CPU_RESET pin exactly do in ZCU106 MPSoC board?

    Hi, I am using ZCU106 MPSoC evaluation board in my designs. Looking at the ZCU106 User Guide, there are multiple reset pins: PS_PROG_B : This action clears the programmable logic configuration, which can then be acted on by the PS software. (To my understanding, this will reset only the PL...
  3. M

    Where is a high-frequency clock capable IO pin in ZCU106 board?

    Hi Guys, I am working with Vivado 2018.2 targeting a ZCU106 board. I am wondering whether there is a high-frequency clock capable IO pin available on the ZCU106 board that I can send out a 250MHz clock signal for monitoring purposes. Preciously, in KC705, I used the USER SMA CLOCK ports...
  4. M

    Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    Thanks @Nikiki for your reply. Can you please elaborate more on this sentence : "make a connection between data stream from DDR to the data buffers inside Zynq" What do you mean data stream from DDR?! You know that DDR has only 1 S_AXI port which is not stream What do you mean by the data...
  5. M

    Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    Hi, I am working wothCicado 3017.3 targeting a zc706 board. I am trying to write some data in the DDR3 of PL and then use AXI DMA (or CDMA, I am a liitlebit confused which one) to read that data from DDR3-PL and write into a Block RAM. My design proposal is like below. I have implemented...
  6. M

    Number of configuration bits used by design in Vivado

    Hi, I am using Vivado 2017.3 targeting a Zedboard with a Zynq FPGA. I have designed and implemented a design and generated the bitstream that works properly. I am wondering whether it is possible to decode the number of configuration bits in FPGA that are used by the implemented design...
  7. M

    How to perform Flash Programming of the ZC706 with our own design files and bitstrea

    Hi niciki, Such a nice explanation! Thank you! I learnt from that. I have encouraged and marked your post as "helpful" becuse you helped me out by your descriptions. Bests, Daryon
  8. M

    How to perform Flash Programming of the ZC706 with our own design files and bitstrea

    Hi Thank you for your reply and nice explanation. Just as a question, should we generate the following files every time in our design or they are some pre-built files and can be downloaded and used for any design? I see these files on github ready for download. I mean these files: FSBL...
  9. M

    How to perform Flash Programming of the ZC706 with our own design files and bitstrea

    Hi, Here are my steps and the relevant printscreens: 1. Implemented design in vivado and generated bitstream 2. export hardware including bitstream and launch sdk 3. Create new application with Zynq FSBL (figure below) 4. From Xilinx/ Create Boot Image, I have defined the path for the new...
  10. M

    How to perform Flash Programming of the ZC706 with our own design files and bitstrea

    Hi, I already saw that page. In that threat, the user tried to run the TRD design offered by Xilinx including their own BOOT>BIN and .elf files. I already could do it successfully. I am trying to program the FLASH memory of ZC706 with my own bitstream which fails!
  11. M

    How to perform Flash Programming of the ZC706 with our own design files and bitstrea

    Hi friends, I am working with Vivado 2017.3 targeting a ZYNQ ZC706 board. I followed the procedure for flash programming of the ZC706 through SD Card in page 13 if this document, and I could successfully see the Xilinx Device in lspci of the Ubuntu terminal. Now, I am wondering how...
  12. M

    In ZYNQ FPGA : Who is controlling the AXI Memory-Mapped to PCI Express module? The P

    In ZYNQ FPGA : Who is controlling the AXI Memory-Mapped to PCI Express module? Dear all, Previously, I was working with Kintex-7 KC705 FPGA board where I was emplyoing the AXI Memory Mapped to PCI Express module with Microblaze to read/write data from/to PCI. Now, I have migrated to ZYNQ...
  13. M

    Why AXI DMAreads only 16 bit from DDR3 instead of 32 bits in my design?

    @std_match, Thanks for your reply. The logic of your hint is correct. The AXI DMA wants to read from DDR3 through MM2S port and write into the BRAM through S2MM port. While I did your hint, I still have the same problem ! Seems to wrird to me! '
  14. M

    Unable to grab PCIe ref_clk for the axi_pcie in ZC706 board !

    Dear all, I am working with Vivado 2017.2 targeting a ZC706 ZYNQ FPGA Board operating on an Ubuntu 16.4 Linux Machine. Previously targeting a Kintex-7 KC705 Board, I was able to choose the PCIe_refclk as the input clock of the buffer in vivadoblock design and use it as the clock signal in...
  15. M

    Why AXI DMAreads only 16 bit from DDR3 instead of 32 bits in my design?

    Dear @ads-ee, Thanks for your reply. AS far as I see in my searches, AXI BFM stands for AXI Bus Functional Model which is available also for the Zynq. However, I could not find any link to order its IP through my Xilinx Account gateway. Do you have any idea about ordering this IP? Thanks
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