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I try to write the finite state verilog program that need to wait sometime in current state before go to next state. I used
example : repeat (10) @(posedge clk);
But error appear like this:
ERROR:Xst:850 - a.v line 32: Unsupported Event Control Statement.
Is there any other...
counter with 7474
I am facing sometime my counter is stuck at 0 during simple 3bits upcounter by using 7474 IC.
After I reconnect again. It is work. It is happen quite often. So I need to clearify myknowledge.
Normally I connect all PREset pins to VCC and all CLeaR pins to switch. When ever...
Re: keypad scan
Dear nand_gates and echo47,
I just try to test my circuit according to both of your advice. I found that my circuit is working properly with pull down circuit (with pull down program code). I still don't know what is the reason behind that.
I just found that my programs are...
Re: How to test CPLD
Logically it seem like that, actually when I test by using simple gates (like or, and )the ports are working properly. But when I used like shift reg or FF there is no response at that port. When I switch to new cpld it work (that means my program is ok.)