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I am sorry for the unclear picture. Here in the image attached, there exist two branches where the current is steered between them simultaneously using NMOS switches in SAT region for minimum glitching.
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I am sorry for the unclear picture. Here in the image attached, there...
I am designing a cascode current mirror for current steering DAC, I have a problem in the glitches that occur at switching (shown in the figure shown), Besides, the current value is not accurate
Designed Current Mirror Specs: Iout=220uA
Vbias=0.6...
This pre. amp. which is used in comp. circuits which are based on +ve feed back ...the higher the difference between the signal and the reference ..the faster your comp. will reach saturation
concerning the operation ..it is a very simple differential pair ...but the input is fully differential...
It is very straight forward .... u just connect ur contoller .... upload ur code at the software ....and it will burn the hex file to ur controller
I recommend using an Arduino board as it will meke ur life much easier :)
I know it is a small note but ...why are u connecting the body of the input transistors to the source, normally we connect the body to the lowest voltage in the circuit
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also the lower transistor, shall be biased by a current source to reject the cm signal
As Electro mentioned .... the Metal layer must be connected to the poly using a via as they are different layers ... the via represents simply a hole to reach a different layer .... always u can check ur design by running the 3d shape to check that all the components are connected correctly
First of all, I'd like to thank you both monsoon and FvM for your help. Actually you were very helpful to me and I really appreciate it.
Second, I am going to re-deign my op-amp again after I understood some fundamental points. So, I just want you guys to explain the relation between both loops...
Please note that I changed the value in the upper circuit (0e5 ) to 40 while doing these plots only, and thanks for your note :)
but I have a question please, Isn't this gain represents both the CMFB gain and the OP-Amp gain ??
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I have reduced my transconductance to 40...
I am designing a two stage op amp with CMFB ,,,but the bode plots of my opamp CMFB loop is totally unstable although the differential bode plots is stable and the output is adjusted correctly by the CMFB to Vdd/2.
Thanks in advance
Please I have one more question concerning this opamp, I will use it as an integrator in a system with a sampling frequency of 384MHZ, so I want my opamp GBW to be about 1GHZ .... I want to know which loop shall be my GBW and determine my PM:
1-Breaking up the CMFB lope using CMDM probe...
Could u please explain more why it is not feasible, as by equations:
For PMOS to be in SAT
Vsd>Vsg-Vth
-Vd > -Vg- Vth
Vd< Vg+Vth
if Vd=0.6, by CMFB at secong stage
Vg>Vd-Vth
-->Vg>0.6-Vth Then according to this point (Vg) can reach Vdd/2.
why it is not feasible then ????
thanks again
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First of all, I'd like to thank u monsoon for ur concern.
Now I implemented the configuration in your comment, the output of the second stage is fixed correctly at 0.6v (I am using 1.2V supply) but the first stage was not fixed ......why does this happen ...although I understand that this point...
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